1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having a fuse portion which is used as, for example, a redundancy relieving circuit or a function adjusting circuit for a mass storage memory, and also to a method of producing the device.
2. Description of the Prior Art
Recently, the fine pattern technique for a semiconductor integrated circuit has been largely advanced. As a result, a memory device configured by a semiconductor integrated circuit, typically, a dynamic random access memory (DRAM) or a static random access memory (SRAM) which has a capacity of a Gbit class has been developed. In order to achieve high integration, wirings for connecting circuit elements are realized by using the multilayer interconnect technology. As the storage capacity of a semiconductor integrated circuit is expanding with the advance of the fine pattern technique, minute dust or the like in the production process causes defective bits which may lower the function of the element or produce a functional failure, whereby the whole of the semiconductor integrated circuit is made defective. This causes a problem in that the production yield is lowered.
As a method of solving the problem, known is a redundancy relief technique. This is a technique of relieving defective bits. In this technique, during a process of producing a chip, spare memory bits are produced in addition to memory bits required in the memory of a product. When there is a defect in a part of the chip and a defective memory bit is therefore produced, the defective memory bit is switched to one of the spare memory bits, so that the whole of the memory bits of a product is configured by non-defective bits. As one of methods of switching a defective memory bit to a spare memory bit, used is a redundancy relief technique based on laser processing in which a fuse portion of a redundancy relieving circuit on a chip is fused and cut off by irradiation with a laser beam, thereby realizing the switching.
In view of simplicity of the production process, conventionally, a material which is mainly composed of polysilicon and silicide that are identical with materials of gate electrodes and bit signal lines of MOS transistors, and polycide configured by laminating polysilicon and silicide is used as a fuse material which is to be laser-processed.
Hereinafter, a fuse portion which is used in a redundancy relieving circuit in the conventional art will be described. FIG. 17 is a section view showing main portions of a conventional semiconductor integrated circuit device. Referring to FIG. 17, 1 denotes a semiconductor substrate, 2 denotes a layer insulating film, 3 denotes fuse portions which are configured by, for example, a polycide layer, 4 denotes an inorganic insulating protective film, 5 denotes an organic insulating protective film, 6 denotes an opening, and 7 denotes a pad electrode which is configured by a metal wiring layer. The pad electrode 7 is an electrode for connecting a lead for package assembling. The organic insulating protective film 5 and the inorganic insulating protective film 4 above the pad electrode 7 are removed away by a usual etching technique so as to form an opening. At the same time, in order to facilitate the cutting of the fuse portions 3 by laser beam irradiation, the organic insulating protective film 5 and the inorganic insulating protective film 4 above the fuse portions 3 are removed away by selective etching to form the opening 6, and a layer insulating film 8 on the fuse portions 3 is thinned.
In a semiconductor integrated circuit device, a multilayer interconnect structure has begun to be employed in order to cope with requirements for high integration and fine patterning. In the configuration of the conventional art, consequently, there arises a new technical problem. Namely, the use of a multilayer interconnect structure causes a large number of wiring layers to exist above a fuse portion which is configured by a polycide layer and the like in the same manner as a gate electrode. As a result, the thickness of the layer insulating film above the fuse portion is increased.
In order to cope with this, by selective etching, an insulating film and a layer insulating film above a fuse portion are removed away and the remaining film is thinned. In order to achieve high integration in a semiconductor integrated circuit device, recently, some multilayer interconnect structures are configured by three or more layers, so that a layer insulating film above a fuse portion has a large thickness. Therefore, the layer insulating film must be etched away by a thickness of about 1 to several μm or more, with the result that the etching removal requires a long time period. This causes the throughput of an etching apparatus to be lowered, thereby producing a technical problem in that the production time period is prolonged. In a large wafer having a diameter of 8 inches or more, furthermore, it is difficult to suppress interfacial unevenness and variation of the etching rate in a etching removal step to a low degree, thereby producing a technical problem in that it is difficult to control correctly and uniformly the thickness of a layer insulating film remaining above a fuse portion, over the whole face of the wafer.